High Cloud Semiconductor launches universal LVDS gearbox interface solution

Foshan, Guangdong, August 22, 2017-Guangdong Gaoyun Semiconductor Technology Co., Ltd. (hereinafter referred to as "Gaoyun Semiconductor") today announced the launch of the GW1N series that supports both the non-volatile small bee® family and the medium density Chenxi® family GW2A A series of general-purpose LVDS gearbox interface IP cores (Gowin Generic LVDS Gearbox IP) of FPGA chips, including related soft cores, reference designs, development boards and other complete solutions.

Gowin Universal LVDS gearbox interface IP realizes the switching of the clock frequency and data bit width between the internal logic and the external interface, and ensures the conservation of data throughput. It also supports the sending and receiving functions. All Gowin FPGA chips receive and send gearbox switching The ratio supports 1: 1, 1: 2, 1: 4, 1: 7, 1: 8, and 1:10. In addition, GW1N-6 / 9 devices also support 1:16 switching ratio. Aiming at the different requirements of the phase relationship between the clock and the data along the way, Gowin Universal LVDS gearbox interface solution supports both edge alignment and middle alignment.

Gowin FPGA chips provide dedicated unit modules for building high-speed LVDS interfaces. According to customer-specific bandwidth, alignment, transceiver functions, and switching ratio requirements, unit modules are integrated and work together to achieve corresponding functions.

· High-speed low-skew clock HCLK is used to support I / O to complete high-performance data transmission;

· GCLK is the internal system clock, and the internal system clock must use the global clock network;

· High-speed clock divider module to generate the divided clock GCLK in phase with the input clock HCLK;

· Phase-locked loop module to achieve clock frequency multiplication, frequency division and phase shift;

· The serial-to-parallel receiving side module realizes the gearbox function;

· Parallel to serial transmission side module to realize the gearbox function;

· Each I / O includes a delay module. The total delay provided is approximately 128 steps x25ps = 3200ps.

"Gowin Universal LVDS gearbox interface IP makes full use of various dedicated unit modules embedded in Gowin FPGA chips, making Gowin FPGA device LVDS I / O interface speed reach 800Mbps to 1.2Gbps performance requirements." Gowin Product Application Manager Mr. Xu Cai explained, “In the TCON market application, the timing action of the LCD screen is controlled by FPGA, and the input video signal, such as LVDS signal, is converted into the form used by the data drive circuit, such as Mini-LVDS or RSDS signal, and passed to the data drive circuit The control data driving circuit is turned on in time, and the Gowin FPGA chip just fits the TCON market demand in terms of the number of LVDS differential pins and LVDS interface performance. "

"The development of video capture and display technology is very rapid. Various video interfaces based on high-speed LVDS interface technology, such as Mini-LVDS, MIPI CSI-2 / DSI, etc., are now widely used in mobile phones, tablet computers, VR, unmanned Applications such as mobile phones, in-vehicle entertainment systems, human-machine interfaces (HMI), etc., the demand for bridging of video interfaces and image processing in user systems has also become more and more. "Huang Huang, Vice President of Marketing of Gao Yun Semiconductor and Sales Director of China Mr. Jun said, "Gaoyun Semiconductor has launched a universal LVDS gearbox interface solution. Combining the advantages of Gaoyun Semiconductor FPGA chips with non-volatility, small and thin packages, and embedded large-capacity SDRAM, it can be used for consumer, automotive electronics and Users of the industrial display market provide video interface bridging and image processing solutions to help users accelerate the time to market. "

The LVDS I / O data rate is currently 1.2Gbps; the internal fabric clock rate is 120MHz for the GW1N series and 200MHz for the GW2A series.

The video image data is converted into parallel video signals by the LVDS 7: 1 receiving module, and converted into the image format required by the LCD screen by the image processing module, and then converted to mini-LVDS signal transmission using the mini-LVDS 4: 1 sending module To the LCD screen.

GW1N / 1NR, GW2A / 2AR series FPGA chips

GW1N / 1NR and GW2A / 2AR series FPGA chips support multiple differential level standards such as LVDS25, RSDS, LVDS25E, BLVDSE, MLVDSE, LVPECLE, and RSDSE. The I / O logic internally integrates a variety of transmission ratio gearboxes.

Gaoyun General LVDS gearbox interface IP, reference design and development board support GW1N-4K FQPF144 packaged FPGA chip pair to connect with LVDS to receive signals and mini-LVDS to send signals, subsequent upgrades will support GW2A series FPGA chips to further enhance LVDS I / O Interface performance.

Guangdong Gaoyun Semiconductor Technology Co., Ltd. was established in January 2014. The company is committed to developing domestic FPGA solutions and promoting its industrialization. It aims to launch national brand FPGA chips with core independent intellectual property rights. The company aims to provide users with the highest quality services, and can provide one-stop services including chips, design software, soft cores, reference designs, and demo boards.

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