lvds interface standard

lvds interface standard:

The LVDS interface is a common interface standard for LCD Panels. Taking 8-bit Panel as an example, it includes 5 groups of transmission lines, 4 of which are data lines, representing Tx0 + / Tx0 -... Tx3 + / Tx3-. There is also a group of clock signals, representing TxC + / TxC-. Correspondingly, there are 5 groups of receiving lines at one end of the Panel. If it is a 6-bit Panel, there are only 3 sets of data lines and a set of clock lines.

LVDS interface, also known as RS-644 bus interface, is a data transmission and interface technology that only appeared in the 1990s. LVDS is a low-voltage differential signal. The core of this technology is to use a very low voltage swing for high-speed differential transmission of data, which can realize point-to-point or point-to-multipoint connection. For low-emission characteristics, the transmission medium can be a copper PCB connection or a balanced cable. LVDS has been more and more widely used in systems that require high signal integrity, low jitter and common model performance. At present, the popular LVDS technical specifications have two standards: one is TIA / EIA (Telecommunications Industry Alliance / Electronic Industry Alliance) ANSI / TIA / EIA-644 standard, and the other is IEEE 1596.3 standard.

In November 1995, the ANSI / TIA / EIA-644 standard was introduced mainly by National Semiconductor Corporation. In March 1996, IEEE published the IEEE 1596.3 standard. These two standards focus on the specifications of the electrical characteristics, interconnection and line termination of the LVDS interface, but are not clear about the production process, transmission medium and power supply voltage. LVDS can be implemented with CMOS, GaAs or other technologies, and its power supply voltage can be from + 5V to + 3.3V or even lower; its transmission medium can be a PCB connection or a special cable. The maximum data transmission rate recommended by the standard is 655Mbps, and in theory, on a lossless transmission line, the maximum transmission rate of LVDS can reach 1.923Gbps.

---- The OpenLDI standard has been widely used in notebook computers. The connection interface between the LCD display and the motherboard of most notebook computers adopts the OpenLDI standard. The basis of the OpenLDI interface standard is the Low Voltage DifferenTIal Signaling (LVDS) interface, which has the characteristics of high efficiency, low power consumption, high speed, low cost, low clutter interference, and can support higher resolution. The LVDS interface is widely used in telecommunications, communications, consumer electronics, automobiles, and medical instruments, and has been supported by companies such as AMP, 3M, Samsung, Sharp, and Silicon Graphics. In order to penetrate into the desktop field, NS has launched new chipsets DS90C387 and DS90CF388 that support the OpenLDI standard specifically for LCD displays. The new chipsets support resolutions from VGA (640 × 480) to QXGA (2048 × 1536) .

---- Although the DVI standard is not as famous as the OpenLDI standard, its application is not as widespread as the OpenLDI standard. However, due to the participation of Intel, IBM, HP and other large companies, the application prospects of DVI are generally optimistic. Some digital CRT monitors, LCD monitors and data projectors have adopted digital display interfaces that conform to the DVI standard.

---- At present, most computers and external display devices are connected through an analog VGA interface. The display image information generated digitally in the computer is converted into R by the D / A (digital / analog) converter in the graphics card. , G, B three primary color signals and line and field synchronization signals, the signal is transmitted to the display device through the cable. For an analog display device, such as an analog CRT display, the signal is directly sent to the corresponding processing circuit to drive and control the kinescope to generate an image. For digital display devices such as LCD and DLP, the corresponding A / D (analog / digital) converter needs to be configured in the display device to convert the analog signal into a digital signal. After D / A and A / D2 conversions, some image details are inevitably lost.

---- The DVI standard was officially launched by DDWG in April 1994, and it is based on PanalLink interface technology of Silicon Image. PanalLink interface technology uses Transition Minimized Differential Signaling (S) as the basic electrical connection. As shown in the figure, the image information generated in the computer is transmitted to the display processing unit (graphics card), processed and encoded into a data signal, which contains some pixel information, synchronization information, and some control information. The information passes through three Channel output. At the same time, there is also a channel for transmitting clock signals that synchronize the sending and receiving ends. The data in each channel is transmitted as a differential signal, so each channel requires 2 transmission lines. Since differential signal transmission is used, both differential pressure signals are identified in data transmission and reception, so the length of the transmission cable has little effect on the signal, and long-distance data transmission can be achieved. At the receiving end, the received data is decoded and processed to generate image information for display by the digital display device. In the DVI standard, the physical mode, electrical specifications, clock mode, coding mode, transmission mode, and data format of the interface are strictly defined and standardized. For digital display devices, since there is no D / A and A / D conversion process, the loss of image details is avoided, thereby ensuring the complete reproduction of computer-generated images. A hot-swap monitoring signal has also been added to the DVI interface standard, thus realizing plug and play

As soon as the DVI standard was launched, it received immediate response. Not only did various graphics chip manufacturers launch a series of chipsets that support the DVI standard, but companies such as ViewSonic and Samsung also successively launched digital CRT monitors and LCD monitors that use the DVI standard interface. We have also seen the DVI standard interface in some recently launched LCD and DLP data projectors. With the advent of the digital age, the DVI standard interface replaces the VGA interface as the de facto standard interface for display devices.

1 Introduction to LVDS
LVDS (Low Voltage Differential Signaling) is a low-swing differential signaling technology that enables signals to be transmitted at a rate of several hundred Mbps on differential PCB pairs or balanced cables. Its low voltage amplitude and low current drive output achieve low Noise and low power consumption.
For decades, the use of 5V power has simplified the interface between different technologies and manufacturers' logic circuits. However, with the development of integrated circuits and the demand for higher data rates, low-voltage power supply has become an urgent need. Reducing the power supply voltage not only reduces the power consumption of high-density integrated circuits, but also reduces the heat dissipation inside the chip, which helps to improve integration.

An excellent example of reducing the supply voltage and logic voltage swing is low voltage differential signaling (LVDS). The LVDS physical interface uses a 1.2V bias to provide a 400mV swing signal (the reason for using differential signals is that noise is coupled in a common mode on a pair of differential lines and subtracted in the receiver to eliminate noise). The LVDS driver and receiver do not depend on a specific power supply voltage, so it is easy to migrate to a low-voltage power supply system without changing performance. For comparison, ECL and PECL technologies depend on the supply voltage. ECL requires a negative supply voltage. PECL refers to the positive supply voltage on the bus (Vcc). The GLVDS is a new technology that has not yet been determined by the developing standard. It can provide a signal swing of 250mV using a power supply voltage of 500mV. The differential voltage swing of different low-voltage logic signals is shown in Figure 1.

LVDS is defined in two standards. IEEE P1596.3 (adopted in March 1996), mainly for SCI (Scalable Coherent Interface), defines the electrical characteristics of LVDS, and also defines the encoding of packet exchange in the SCI protocol; ANSI / EIA / EIA-644 (1995 Passed in November), which mainly defines the electrical characteristics of LVDS, and proposes a maximum rate of 655Mbps and a theoretical limit rate on a distortion-free medium of 1.823Gbps. Both standards specify characteristics that are not related to physical media, which means that as long as the media sends signals to the receiver within the specified noise margin and skew tolerance, the interface will work properly. LVDS has many advantages: ① easy terminal adaptation; ② low power consumption; ③ with fail-safe features to ensure reliability; ④ low cost; ⑤ high-speed transmission. These characteristics make LVDS widely used in computers, communication equipment, consumer electronics, etc.
Figure 2 shows a typical LVDS interface. This is a simplex mode. Half-duplex, multi-point configuration can also be used when necessary, but it is generally applicable when the noise is small and the distance is short. Each point-to-point differential pair consists of a driver, interconnector, and receiver. The driver and receiver mainly complete the conversion between TTL signals and LVDS signals. The interconnector includes cables, differential wire pairs on the PCB, and matching resistors. The LVDS driver consists of a current source that drives differential pairs? Usually the current is 3.5mA). The LVDS receiver has a high input impedance, so most of the current output by the driver flows through the matching resistor of 100Ω? The input terminal generates a voltage of approximately 350mA. When the driver flips over, it changes the direction of the current flowing through the resistor, thus producing valid logic "1" and logic "0" states. The low-swing drive signal enables high-speed operation and reduces power consumption, and the differential signal provides a low-voltage swing with appropriate noise edges and greatly reduced power consumption. The large reduction in power allows multiple interface drivers and receivers to be integrated on a single integrated circuit. This improves the efficiency of the PCB board and reduces costs.

Regardless of whether the LVDS transmission medium used is a PCB wire pair or a cable, measures must be taken to prevent signal reflection at the media terminal while reducing electromagnetic interference. LVDS requires the use of a termination resistor (100 ± 20Ω) that matches the medium. This resistor terminates the circulating signal and should be placed as close as possible to the input of the receiver. The LVDS driver can drive twisted pair at a speed of more than 155.5Mbps, the distance is more than 10m. The actual limitations on speed are: ① the speed of the TTL data sent to the drive; ② the bandwidth performance of the media. Usually multiplexers are used on the driver side and demultiplexers are used on the receiver side to achieve multiplex conversion of multiple TTL channels and one LVDS channel to increase the signal rate and reduce power consumption. And reduce the number of transmission media and interfaces, reduce the complexity of the equipment.
The LVDS receiver can withstand at least ± 1V of the ground voltage between the driver and the receiver. Since the typical bias voltage of the LVDS driver is + 1.2V, the sum of the voltage variation of the ground, the driver bias voltage, and the noise that is slightly coupled to it is a common-mode voltage at the input of the receiver relative to the ground of the receiver. The common mode range is: + 0.2V to + 2.2V. It is recommended that the input voltage range of the receiver is: 0V ~ + 2.4V.
2 Design of LVDS system
The design of the LVDS system requires that the designer should have experience in ultra-high-speed single-board design and understand the theory of differential signals. It is not very difficult to design a high-speed differential board. The following points will be briefly introduced.
2.1 PCB board
? (A) Use at least 4 layers of PCB board (from top layer to bottom layer): LVDS signal layer, ground layer, power layer, TTL signal layer;
(B) Isolate the TTL signal and the LVDS signal from each other, otherwise the TTL may be coupled to the LVDS line, it is best to place the TTL and LVDS signals on different layers separated by the power / ground layer;
(C) Make the LVDS driver and receiver as close as possible to the LVDS end of the connector;
(D) Use distributed multiple capacitors to bypass the LVDS device, and place the surface-mounted capacitor close to the power / ground pin;
(E) The power layer and ground layer should use thick wires, and do not use 50Ω wiring rules;
(F) Keep the return path of the PCB ground layer wide and short;
(G) Cables using gu9ound return wire should be used to connect the ground of the two systems;
(H) Use multiple vias (at least two) to connect to the power layer (wire) and ground layer (wire). Surface-mount capacitors can be directly soldered to the via pads to reduce wire ends.
2.2 On-board conductor (A) Microwave transmission line (microstrip) and stripline (stripline) have better performance;
(B) The advantages of microwave transmission lines: generally have higher differential impedance and do not require additional vias;
(C) Stripline provides better shielding between signals.
2.3 The differential line (A) uses a controlled impedance line that matches the differential impedance and termination resistance of the transmission medium, and makes the differential line pairs as close as possible to each other as soon as they leave the integrated chip (distance less than 10 mm), which can reduce reflection and Can ensure that the coupled noise is common mode noise;
(B) Match the length of the differential pair to reduce signal distortion and prevent the phase difference between the signals to cause electromagnetic radiation;
(C) Do not rely solely on the automatic wiring function, but should be carefully modified to achieve differential impedance matching and achieve differential line isolation;
(D) Minimize vias and other factors that cause line discontinuities;
(E) Avoid the 90 ° traces that lead to resistance discontinuity, use arcs or 45 ° polylines instead.
(F) Within a differential pair, the distance between the two lines should be as short as possible to maintain the receiver ’s common-mode rejection capability. On the printed board, the distance between the two differential lines should be as consistent as possible to avoid the discontinuity of the differential impedance.
2.4 The terminal (A) uses a terminal resistor to achieve the maximum matching of the differential transmission line. The resistance value is generally between 90 and 130 Ω. The system also requires this terminal resistor to generate a normally working differential voltage;
(B) It is best to use a surface-mount resistor with an accuracy of 1 to 2% across the differential line. If necessary, you can also use two resistors each with a resistance of 50Ω, and ground it through a capacitor in the middle to filter out the common mode. noise.
2.5 Unused Pins All unused LVDS receiver input pins are left floating, all unused LVDS and TTL output pins are left floating, connect unused TTL send / driver input and control / enable pins to power or ground .
2.6 Selection of media (cables and connectors) (A) Use of controlled impedance media with a differential impedance of approximately 100 Ω, without introducing large impedance discontinuities;
(B) Only in terms of reducing noise and improving signal quality, balanced cables (such as twisted pairs) are usually better than unbalanced cables;
(C) When the cable length is less than 0.5m, most of the cables can work effectively. When the distance is between 0.5m and 10m, the CAT 3 (Categiory 3) twisted pair has a good effect on the cable, it is cheap and easy to buy, and the distance is greater than When 10m and high speed are required, it is recommended to use CAT 5 twisted pair.
2.7 Improve reliability design in noisy environment
The LVDS receiver internally provides a reliability circuit to protect the output reliability when the receiver input is floating, the receiver input is shorted, and the receiver input is matched. However, when the driver is tri-stated or the cable on the receiver is not connected to the driver, it does not provide reliability guarantee in a noisy environment. In this case, the cable becomes a floating antenna. If the noise induced by the cable exceeds the tolerance of the LVDS internal reliability circuit, the receiver will switch or oscillate. If this happens, it is recommended to use balanced or shielded cables. In addition, a resistor can be added to increase the noise margin, as shown in Figure 3. In the figure, R1 and R3 are optional external resistors to improve the noise tolerance, R2≈100Ω.

Of course, if the LVDS transceiver embedded in the chip is used, since there is generally a mechanism to control whether the transceiver works, this suspension will not affect the system.
3 Application examples
LVDS technology is currently widely used in high-speed systems. This article gives a simple example to look at the specific connection method. Canadian PMC's DSLAM (Digital Subscriber Line Access Module) solution uses LVDS technology to achieve point-to-point single-board interconnection. The system structure is very scalable, achieving high integration on the line card, and fully able to meet business decentralization 1. The requirement of large amount of business data and control flow communication brought by control concentration.

Figure 4 describes the connection between the line card and the line card, and between the line card and the backplane of the system. The simplex mode is used, so two pairs of lines are required to achieve two-way communication. The figure shows three different connection methods, from top to bottom: there is a corresponding connection chip; terminal matching when cross-rack; terminal matching when the same layer of chassis. Connecting a transformer in series at the receiving end can reduce interference and avoid the influence of the large potential difference between the LVDS driver and the receiver. LVDS interface definition.